1. Field of the Invention
The present invention relates to semiconductor memories and, in particular, to use of a CMOS differential latch with a tristate buffer to create a sense amplifier with optimum speed and power with tristatability.
2. Discussion of the Prior Art
A sense amplifier detects low-level signals received from the cells of a memory array and converts these signals to levels compatible with the rest of the system in which the memory is used.
As memory density increases, the memory cell size and the corresponding cell output signal is reduced, thereby making the sense amplifier critical for high speed applications. The sense amplifier should be highly sensitive and still meet the speed requirements of the high density memories.
A conventional sense amplifier detects the memory cell output through a differential amplifier, which is highly sensitive, but has very small voltage gain. The sense amplifier requires a biasing circuit which burns static power and is also supply voltage and process sensitive.
FIG. 1 shows a conventional differential sense amplifier of the type generally used in most CMOS VLSI memory circuits. The differential sense amplifier includes n-channel transistors T1 and T2 which comprise a differential pair and n-channel transistor T3 which is a biasing transistor driven by biasing circuit 5. Currents I1 and I2 are the supply currents for the differential pair transistors T1 and T2, respectively. Node 7 of transistor T3 is biased in such a way that the voltage at node 6 is maintained at an optimum voltage to optimize speed and sensitivity.
As further shown in FIG. 1, input signals W1 and W2 are applied to the respective input nodes 1 and 2 of the differential amplifier. The input nodes 1 and 2 are capacitively decoupled from the output driver nodes 3 and 4, which have large capacitive loads C3 and C4, respectively.
The biasing circuit 5 is a static circuit, which takes DC power. Its output voltage, which is provided at node 7, is dependent upon supply voltage and process parameters which in turn control the voltage at node 6.
Referring concurrently to the FIG. 1 schematic diagram and its associated FIG. 2 signal waveforms, during the operation of the FIG. 1 circuit, input signals W1 and W2 are applied to the low capacitance input nodes 1 and 2; the output nodes 3 and 4 can be either W3 and W4 or W5 and W6 depending upon the voltage at node 6. The lower the node 6 voltage, the higher the voltage gain; however, it will be slower (as W3 and W4). On the other hand, when the node 6 voltage is higher, i.e., close to the input signal levels, the sense amplifier will be very sensitive but have smaller voltage gain (as W5 and W6).
For the case where the output signal W3 and W4 on nodes 3 and 4, respectively, is larger, but slower by dt1 compared to output signal W5 and W6, where the output signal (W5 and W6) is smaller, but faster by dt2 as indicated.
Thus, it is clear that there is a tradeoff between the signal delay in the differential amplifier to the voltage gain (differential output voltage/differential input voltage). As stated above, this trade-off is primarily controlled by the voltage at node 6, which in turn is controlled by biasing circuit 5 through biasing transistor T3. This indicates that any biasing voltage fluctuations clearly impact the voltage gain as well as the input to output delay in the differential sense amplifier.
It can also be seen from both the high gain, less sensitive and the low gain, very sensitive cases that the output signal pairs W3, W4 and W5, W6 will never reach full rail supply voltages. When these signals drive the next stage, DC power will be burned, which further increases the DC standby or active power.